The present invention relates to the field of electronic circuitry, and more particularly, to electronic circuitry for interfacing a microprocessor with a microcontroller or another microprocessor.
Many different types of microprocessors and microcontrollers are often combined with other types of circuitry in a single circuit in an attempt to provide specialized microprocessor circuitry capable of efficiently executing a preselected set of functions. For example, a general purpose microcontroller or microprocessor may be used to oversee and control the general operations of the circuitry, while a general purpose or specialized digital signal processor may be employed to perform special signal processing functions, such as, for example, data compression or decompression, data encryption or decryption, and signal modulation or demodulation. Many different methods may be employed to allow for interconnection between such a microcontroller or microprocessor (e.g. a host processor) and a digital signal processor which allow the digital signal processor to perform its functions under the control of the host processor. For some circumstances the host processor may also be a digital signal processor.
One such method is to provide a so-called host port connection between the host processor and the digital signal processor. Such a host port connection typically allows for the interchange of data and/or program code between the two processors. However, the currently known and used host ports are not designed to effectively interconnect a wide variety of processors or to provide performance of selected functions in a power efficient manner or with a minimized chip or layout size.
Thus, there are still unmet needs for circuitry capable of interfacing a microprocessor with a host microprocessor in more a efficient and/or effective manner.
According to one aspect of the present invention, a circuit for interfacing a microprocessor with a host microprocessor in an efficient and effective manner is provided. In a presently preferred embodiment, a circuit for interfacing a processor with a host processor has a memory associated with said processor that is selectively accessible by both said processors or by said host processor, a plurality of storage devices selectively interconnectable with said memory and said host processor, and a logic circuit interconnected with said storage devices and processors for interconnecting at least a portion of said storage devices to said memory in response to signals from said processors.
The present invention provides circuitry for interfacing a processor with a host processor and which circuitry has clock circuitry for generating clock signals synchronous with clock signals from said processor and for generating clock signals based on signals from said host processor that are asynchronous with said clock signals from said processor, first logic circuitry clocked by said synchronous clock signals for generating synchronous memory access control signals, second logic circuitry clocked by said asynchronous clock signals for generating asynchronous memory access control signals, and a register for storing preselected control signals.
The present invention provides circuitry for interfacing a microprocessor with a host microprocessor, which circuitry has a memory accessible by said microprocessors, a memory interface circuit interconnected with said memory, a plurality of data latches interconnectable with said memory interface, a plurality of address registers interconnectable with said memory interface, a control register for storing preselected control signals, a bus interconnected with said latches, said registers, and said host processor, and a control circuit interconnected with said latches, registers, bus and control register for appropriately interconnecting said latches or registers to said memory in response to control signals from said processor or said host processor.
The present invention provides circuitry for controlling the testing of a circuit having portions using either synchronous or asynchronous clock signals having a first multiplexer for selectively providing said synchronous clock signal or a test clock signal to said portion of said circuit using said synchronous clock signal, and a second multiplexer for selectively providing the output from said first multiplexer or said asynchronous clock signal to said portion of said circuit using said asynchronous clock signal.
The present invention provides an integrated circuit having a microprocessor, a memory associated with said processor that is selectively accessible by said microprocessor or a host processor, a plurality of storage devices selectively interconnectable with said memory and said host processor, and a logic circuit interconnected with said storage devices and interconnectable with said processors for interconnecting at least a portion of said storage devices to said memory in response to appropriate signals from said processors.
The present invention provides circuitry for interfacing a processor with a host processor.
The present invention also provides a system for controlling the testing of a circuit having portions using either synchronous or asynchronous clock signals.